Fabrication of semiconductors typically comprises many steps, including creation of a silicon wafer, deposition of various materials onto the wafer, ion implantation into the wafer, etching away material applied to the wafer, and other similar processes. These processes are used to create the electronic components and connections on the wafer that form a useful electronic circuit.
As these processes are performed on the wafer, the wafer might be subjected to parametric testing. Parametric testing involves testing the electronic parameters of the circuitry on the wafer, such as by applying current or voltage, and by measuring resistance, capacitance, current, voltage, circuitry shapes, circuitry distances, or other such electrical parameters. These tests are used to ensure that a fabricated structure on the semiconductor meets the specifications and requirements of the semiconductor manufacturer and falls within acceptable tolerances.
Parametric testing can take place during the fabrication process to ensure that each stage of fabrication is successful, and is usually performed on the completed wafer to ensure that each completed circuit on the wafer is functional and meets specified performance criteria.
This parametric testing is typically performed with a parametric test system, which is comprised of several parts. Such systems might be capable of loading a wafer from a wafer tray to a wafer chuck, which is then properly alignment under a test pin by a wafer positioner. Once the equipment has properly loaded and positioned the wafer, parametric test instrumentation systems are initialized and operated to apply electrical signals, heat, and other stimuli as needed to the wafer. The test instrumentation also measures parameters, such as impedance and current or voltage measurement, and the test system then analyzes and records the results of the parametric tests.
Although parametric testing is typically used to verify the parameters or performance of production semiconductors, such testing can also be critical in investigating the usability or performance characteristics of new materials or new circuit structures. A wide variety of tests, including resistance, capacitance, transistor characteristic, thermal characteristic, and other tests enable characterization of these new materials and circuits, as well as verification of performance in a production environment.
Testing a single wafer can involve tens of thousands of measurements per wafer, with dozens of wafers per manufacturing lot or wafer tray loaded for test. Because this results in literally millions of parametric tests and measurements that must be performed per wafer lot, the time that such testing requires is an important factor in the productivity of a wafer or semiconductor fabrication facility.
Typically, testing is defined by test maps associated with predefined test plans that are developed by specialized staff, such as semiconductor engineers. Often, these engineers have a wealth of knowledge and experience that is not properly leveraged within an organization. Moreover, their knowledge and experience are often completely lost when engineers leave the organization.
Furthermore, predefined testing sessions are set aside for equipment access, which is required to test a wafer lot. If an engineer detects an area within a wafer that needs more thorough investigation during a testing session, then any additional tests that may be needed are delayed, developed, and processed during a different testing session, and the existing static tests are executed during the allotted testing session. This entire process is time consuming, static, and often unnecessarily duplicated.
For these reasons, there is a need to dynamically operate semiconductor parametric tests on wafers, thereby minimizing the use of development resources and processes during predefined testing sessions. Moreover, tests should be reusable and should enhance existing capabilities that verify performance characteristics of wafer structures under test.